Analog Devices
Newbury
At the Newbury design centre, I joined the AMS design team working on ADI's next generation "high-speed precision" ADC. When I joined the team, the project was moving out of the design phase into the chip verification phase. Therefore, I had to quickly get up to speed with the in-house simulation tools and scripting language. Once I was up to speed, I was able to move on to more involved verification tasks - from block level testing to full system simulations at the top chip level. ADC's exist on the analogue/digital boundary, which means that AMS designers need to have strong foundations in both analogue and digital design. It was a really interesting experience to learn about the complexity of modern ADC's, and to get an insight into the wide-range of skills that are required of IC design engineers.
My placement started with verifying the functionality of a reference detection subcircuit, which taught me how to design testbenches, setup simulation scripts, and run a variety of simulations over process corners. Once I had verified the functionality of the block over a range of conditions, I curated a design review for the block which I presented to the design team. Since that project, my main responsibility has been to run EM (electromigration) and aging simulations on completed blocks. If a track has been designed too narrow given the amount of current flowing through it, an ADI proprietary simulation tool is able to flag a current density violation and provide information on the nature of the violation (e.g. location, metal layer, over-current ratio). Then, it is my job to report any of these violations back to the layout team so that problems can be amended. This task gave me the opportunity to gain more familiarity with navigating chip layout and even identifying amendments to reduce stresses on nets. The chip manufacturer provides aging information on FET devices associated with the process node used to design the chip, which describes how the performance of devices will degrade under certain I-V conditions. I have taken the responsibility of running aging simulations on blocks, to ensure that the I-V conditions in steady operation and startup/power-down will not result in the performance of blocks degrading prematurely.
Designing Cadence testbenches, running simulations, navigating chip layout, extracting layout netlists, extracting s-parameter models, Linux.
Communication, technical presentations, punctuality.