Alpha and Omega Semiconductor
Bishops Stortford
This placement was focused on improving the digital power controller architecture for a multiphase buck voltage regulator. Initially I spent time learning about the converter and its unique behaviour, and then attempted to reimplement the plant and controller in octave to help with prototyping designs down the road. I then helped switching from running analog simulations of the converter and controller into running a digital simulation, which would allow us to run simulations in a much shorter time. Once I had learnt and understood the system well enough, I started improving the design of the load current observer by implementing dynamic capacitance recalculations on hardware, and then using those capacitance values to recalculate the eigenvalues of the observer each controller tick. After creating a model on cadence that uses real values (doubles and floats), I ported this design into the fixed point domain to allow for much faster calculations. The finalised optimised architecture was synthesised through genus where we closed timing at 180MHZ. Finally I started work on a “blue skies” project which was to redesign the controller for a digital implementation only. After carrying out some bibliography to see what other people had created and not to recreate something someone had already done, I settled on an LQR controller with integral action which is great for multi input multi output systems such as ours.
I am a digital design/control/systems architect intern and I have helped optimise tight calculations on fpga fabric. As an example, the critical path of the load current observer I mentioned earlier was a multiplexer, a multiplier, a bit shift, an addition and one more mux, all in 1 clock cycle running at 180MHZ. This also required me to calculate all the fixed point widths I would need, as an example the feedback voltage would be 14 bits, and I would have to decide how many fractional/integer bits I need and design my coefficients based on that. As a digital designer I also have to verify my design would work on actual hardware, which we can do via post synthesis simulations that include the timing files generated during synthesis. On the control side, I have researched into different control techniques that others have completed, such as sliding mode and explicit model predictive control and then landed on using LQR with integral action as a unique implementation that others haven’t researched into.
Although I had an understanding of system Verilog before this placement, I still treated it similar to a traditional linear programming language such as C++. Doing this placement has given me much more exposure to it letting me truly separate system Verilog from a linear language and force me to use its parallel capabilities. If I still want to utilise linear programming, I can always instantiate a finite state machine but what I do on Verilog I cannot in a traditional language. Ive been using industry level tools such as Cadence Simvision for simulations and Genus for synthesising, and have gotten used to the Linux environment as well, being able to navigate smoothly, and create simple scripts to start simulations. I have also learnt lots about modelling systems. Although I have only modelled a buck converter, the flow is similar for many other kinds of systems.
Every week we would hold an internship meeting where I would present my work to the working team at AOSMD. I had to explain what I was working on that week, what challenges I faced, if and how I overcame then and finally what my plans for next week were. This helped me with my presenting and communication skills.