Huawei Technologies Research & Development (UK)
Cambridge, UK
My 6-month industrial placement was with the CPU Architecture Department at Huawei R&D Cambridge. In modern chip design, physically manufacturing hardware prototypes to test new architectural designs is incredibly expensive and time-consuming. To address this, computer engineers rely heavily on specialized software tools called simulators. These simulators mimic the exact behaviors of next-generation processors before they are built in silicon. The main objective of my placement was to contribute to the performance evaluation and optimization of these core simulation tools, ensuring they can accurately model future processing requirements and help the design team identify potential hardware bottlenecks early in the development cycle. This experience perfectly bridged the gap between academic computer architecture theory and real-world commercial hardware engineering.
I maintain technical ownership of deploying experimental architectural features onto the TLB simulator and expanding its performance telemetry. To analyze microarchitectural tradeoffs, I introduced custom performance counters and statistics-gathering capabilities. Furthermore, I executed extensive trace generation and execution runs across both single-core and multi-core scenarios to evaluate heavy-load server benchmarks and throughput limits. To streamline data analysis, I developed an automated script feature that parses raw benchmark telemetry and directly compiles it into visual statistics during trace execution. Another major contribution is the comprehensive refactoring of the simulator's testing infrastructure. By overhauling the unit testing framework, I significantly accelerated unittest execution speeds and optimized regression detection capabilities. Throughout these tasks, I closely collaborated with my mentor during daily and weekly synchronization meetings to align test plans and ensure complete edge-case coverage.
I significantly advanced my practical engineering and system-level modeling capabilities. In software development, I regularly utilized Linux environments, Git version control, and VS Code for managing complex simulator codebases and workspace configurations. Architecturally, I developed a deep understanding of processor memory subsystems, specifically focusing on memory simulation techniques, hardware trace generation, and full-system emulation via QEMU plugins. I enhanced my automation and data-processing skills by writing custom scripts to handle massive server benchmark telemetry and compile statistics into visual data charts. Finally, I mastered industry-standard test engineering methodologies. This includes designing robust test cases, constructing comprehensive test plans to rigorously target complex edge cases, and overhauling testing infrastructures to optimize regression detection and maximize simulation efficiency
The placement provided a robust structure for workload planning and key insights into bridging academic theory with practical engineering. Operating within an agile model with daily and weekly alignment meetings, I collaborated within an internationally diverse team, exposing me to varied perspectives ranging from pure research concepts to concrete production constraints. This rigorous environment emphasized complete validation, teaching me to construct test plans targeting complex edge cases. My communication skills improved significantly; I learned to convey granular technical trace data to the core Memory team while translating these metrics into high-level system impacts for management reviews. Crucially, my mentor’s guidance pushed me to maintain a holistic view, evaluating how specific memory simulator modifications influence the entire memory sub-system rather than analyzing components in isolation.