Citadel Securities
Hong Kong
Having recently completed my six-month industrial placement, I can fully recognize how profoundly the experience has shaped my engineering standards and career aspirations. As part of my degree, I had the opportunity to work as a FPGA Engineering Intern at a leading global financial technology firm. My overarching objective was to translate theoretical university concepts into high-performance industry solutions. Specifically, my mission focused on extending the functionality of existing production systems by migrating complex software-based processes directly into custom hardware to achieve significant latency reductions. Beyond the technical scope, my placement was defined by a deeply collaborative and intellectually stimulating culture. The firm places a genuine investment in mentorship and employee growth, ensuring I always had the exact tools and support necessary to operate effectively. I was empowered to make a tangible impact from day one, which has definitively solidified my desire to pursue a career in low-latency FPGA engineering.
Throughout my placement, I was trusted to take end-to-end ownership of critical hardware design projects, primarily focusing on migrating software-based systems into custom hardware to significantly reduce processing latency. Because the nature of this work was highly exploratory, I had the opportunity to investigate multiple viable solutions rather than working from a rigid specification. I was responsible for systematically evaluating these different approaches, analyzing the trade-offs in performance and physical resource utilization, and ultimately making the final call on the architectural direction. Collaborating closely with cross-functional teams, I acted as a bridge to efficiently map complex algorithmic models into physical hardware. I am incredibly grateful for the autonomy I was given to actively drive design scoping, refine system specifications, and proactively propose optimized solutions, knowing that my engineering judgment was genuinely trusted and valued by the wider team.
This placement significantly expanded my technical toolkit, forcing me to dive deep into advanced hardware optimization techniques. I learned how to write "smart", hardware-aware RTL code that physically maps out logic circuits to process data as efficiently as possible. A major technical skill I developed was optimizing complex designs to operate at highly aggressive processing speeds. This involved an iterative process of analyzing how data flows through an FPGA and manually restructuring those physical pathways to alleviate localized congestion and meet strict performance targets. Additionally, I gained extensive experience in rigorous hardware testing and system-level integration. I learned how to break down massive volumes of diagnostic data to make informed structural fixes. Furthermore, I developed strong practical skills for debugging directly in the hardware labs, utilizing specialized techniques to rigorously prove design correctness and accurately measure system performance on physical FPGAs.
The most impactful non-technical skill I developed was cross-functional communication. Discussing hardware trade-offs such as processing speed versus resource efficiency with stakeholders who operate at entirely different levels of the technology stack dramatically refined my ability to operate as a cohesive member of a multi-disciplinary organization. I also developed a strong sense of accountability. Because my projects were highly exploratory, I had to independently drive the research, make final calls on architectural features, and confidently defend my decisions. Crucially, my time here shifted my engineering mindset; I learned to actively challenge underlying assumptions rather than blindly accepting requirements, always evaluating whether a proposed solution was genuinely necessary. Finally, I focused heavily on maintainability and knowledge transfer, producing clean, highly transparent documentation so future engineers can easily understand the design's trade-offs and build upon it without navigating hidden technical debt.