Apple
London
Working on pre-silicon hardware verification of a specific component within in the GPU to ensure the hardware functions as intended. The overall goal is to simulate the GPU extensively under stressful conditions to find and resolve bugs before the highly expensive physical manufacturing process begins.
- Enhanced stimuli to aggressively stress-test RTL, exposing bugs that led to design fixes - Wrote functional coverage to ensure the stimulus was exercising interesting system states as intended
- SystemVerilog and UVM: wrote SystemVerilog code and learned UVM architecture to build simulation-only components - Functional coverage: learned to write and analyse coverage metrics to quantify how much of the hardware's features and boundary conditions have been successfully tested - Test generation: learned how to balance automated, constrained random testing with highly specific directed tests to force the design into rare edge cases - Debugging and analysis: analysed log files and wave outputs to trace root causes of failures and determine if they were testing errors or genuine design flaws
Cross functional communication: collaborated with different specialised engineering teams e.g. RTL designers, formal verification engineers, micro-architects - to gain the necessary knowledge needed to tackle the problems I was solving. I developed the ability to ask precise & targeted questions to domain experts to piece together their individual knowledge into a cohesive mental model of the system. Adaptability: learned the importance of adaptability in the fast paced tech industry by successfully pivoting my verification strategy several times as required.